Courses & Academic Work 📘
A curated collection of my coursework at IIT Bombay.
- EE 789 — Algorithmic Design of Digital Systems
Introduced to Petri Nets and their advantages over traditional FSMs, followed by a detailed study of AHIR’s dataflow-based design model. Explored AHIR building blocks, their VHDL realizations, and applied them to digital system design through practical examples. - EE 748 — Advanced Topics in Computer Architecture
This research-intensive course builds on SMT and GPGPU architecture, diving into advanced topics such as heterogeneous ISAs, reconfigurable CMPs, TLB prefetching, fault-tolerant redundant execution, and look-ahead architectures through discussions of ISCA and MICRO papers. - EE 739 — Processor Design
Covers the evolution of computers, microprocessor architecture, instruction execution (FSMs, pipelines), memory systems, caching, branch prediction, and superscalar/VLIW execution. Also includes virtual memory, process scheduling, cache behavior, parallelism, and multithreading for modern high-performance processor design. - EE 709 — Testing & Verification of VLSI Circuits
Covers Boolean algebra, VLSI design flow, formal verification, BDD/SAT-based reasoning, equivalence checking, and fault modeling for testing digital circuits. Focuses on automated techniques that ensure correctness and reliability of combinational and sequential hardware designs. - EE 705 — VLSI Design Lab
EE705 focuses on practical VLSI design through Verilog-based implementation of arithmetic units, memory systems, and a complete RISC-V processor pipeline. The course emphasizes full RTL-to-FPGA flow, including simulation, synthesis, debugging, and SoC integration using Vivado and PYNQ hardware. - EE 678 — Wavelets
Introduces the fundamentals of wavelet transforms, key families like Haar and Daubechies, the uncertainty principle, and comparisons with STFT. Covers multilevel decomposition using high/low-pass filters and perfect reconstruction of signals from wavelet coefficients. - EE 677 — VLSI CAD
Covers the full VLSI design flow including logic minimization, fault detection algorithms, and physical design steps such as partitioning, placement, and routing. Emphasizes practical heuristics and fault-modeling techniques used to optimize circuit correctness, testability, and layout efficiency. - EE 671 — VLSI Design
This course covers CMOS device fundamentals, logic gate design, latches/flip-flops, arithmetic units, FSM-based control paths, and memory architectures ranging from ROMs to SRAM/DRAM. It also introduces multi-stage logic optimization, semi-custom VLSI design styles (PLAs, FPGAs), I/O circuits, packaging, and testing methodologies. - EE 669 — VLSI Technology
This course covers the complete VLSI process flow—from wafer cleaning, oxidation, diffusion, implantation, lithography, CVD/PVD deposition, plasma/RTP processing, interconnect fabrication, to full NMOS/CMOS/Bipolar process integration. It also explores advanced device technologies including high-k/metal-gate stacks, multi-level metallization, and modern nanoscale architectures such as FinFETs and GAAFETs down to 3 nm. - EE 451 — Supervised Research Exposition
Short course summary here. - EE 344 — Electronic Design Lab
Projects in this lab course span various areas within the electrical engineering domain such as electronic systems, computational processing, IOT, power systems, control systems with the objective of delivering a working prototype by the semester end - EE 309 — Microprocessors (CISC & RISC)
The course covered instruction set architectures, 8085/8051 microprocessors, assembly programming, timers, interrupts, delays, and peripheral interfacing. It also explored RISC vs. CISC architectures, multi-cycle and single-cycle CPUs, pipelining, and cache memory. - DH 607 — Introduction to Computational Multi-Omics
The course bridges biology, statistics, and computing to teach how modern sequencing technologies generate high-dimensional genomic data and how mathematical models help extract meaningful biological insights. It covers sequence alignment, gene expression analysis, dimensionality reduction, statistical modeling of multi-omics data, and practical skills for exploratory analysis, visualization, and reproducible bioinformatics workflows.
EE 789 — Repository Info
📦 Repository:
This repository contains all coursework for EE789: Algorithmic Design of Digital Systems 📘, including the Final Project, Midsem Assignment, and Mini Project.
The Final Project implements three matrix multiplication architectures ⚙️—unrolled dot product, block-parallel computation, and rank-1 decomposition—using Algorithmic Assembly with detailed analysis.
The Midsem Assignment focuses on VHDL-based arithmetic units ➗ such as multipliers, dividers, and square-root units, complete with Vivado testbenches and reports.
The Mini Project builds a 4×4 Output-Queued Switch 🔀 featuring fair arbitration, packet routing, and structured queuing using AHIR dataflow principles.
Each module includes source code, architecture diagrams, simulation results, and documentation 📄.
Toolchain includes Vivado, VHDL, GTKWave, and Algorithmic Assembly 🛠️.
EE 748 — Repository Info
📦 Repository:
This repository contains all coursework for EE748 — Advanced Topics in Computer Architecture 🧠, including assignments, research paper reviews, gem5 experiments, and a superscalar processor project.
Assignments cover SPEC benchmark analysis 📊, LLC sensitivity studies, and custom cache replacement policy design.
Further work explores RVCF-guided branch prediction 🔍 using leading/trailing core simulations in gem5 to improve accuracy and IPC.
The superscalar project implements an out-of-order processor in Verilog ⚙️ with register renaming, ROB, reservation stations, and full pipeline evaluation.
The course project proposes GPU optimizations by combining NL-DWF with register prefetching 🚀 to reduce RF conflicts and improve SIMD efficiency.
A comprehensive set of research paper reviews 📚 spans heterogeneous ISAs, fault tolerance, branch prediction, secure architectures, and cache innovations.
Together, this repository demonstrates extensive architectural analysis, simulation, and hardware-software co-design skills.
EE 739 — Repository Info
📦 Repository:
This repository for EE739 — Processor Design contains complete implementations of both an Out-of-Order and an In-Order Superscalar Processor, built using Verilog and VHDL 🚀.
The OoO design features reservation stations, ROB, unified register file, ALUs, LSUs, hazard control, and dual-issue execution, supporting in-order commit and broadcast forwarding.
The repository includes full datapaths, controller logic, fetch/decode stages, register files, load/store buffers, and testbenches 📁.
The In-Order superscalar processor implements parallel pipelines, scoreboard-based hazard detection, modular execution stages, and ISA-compliant components 🔧.
Together, these designs demonstrate strong understanding of pipelined execution, register renaming, scheduling, hazard management, and ILP in modern processor architectures 🧠.
EE 709 — Repository Info
📦 Repository:
This repository contains all assignments for EE 709: Testing & Verification of VLSI Circuits, focusing on ROBDD-based modeling and ATPG workflows.
It includes state-machine encoding, Boolean function analysis, output-space feasibility checking, and ROBDD-driven equivalence verification.
The ATPG section features fault equivalence classification, SAT-based test pattern generation, and deductive fault simulation for stuck-at defects.
Problems cover invertibility checks, impossible-output detection, and analysis of structural faults using Minisat.
Overall, the repository demonstrates formal verification methods and automated testing techniques used to validate and ensure correctness of digital hardware.
EE 705 — Repository Info
📦 Repository:
This repository contains all Verilog-based assignments and projects from EE 705: VLSI Design Lab, covering arithmetic units, memory subsystems, and a complete RISC-V 32IM processor implementation. ⚙️💻
It includes designs such as Brent–Kung adders, Dadda multipliers, barrel shifters, and custom I-/D-cache architectures, all validated through simulations and FPGA runs. 🔧📐
The RISC-V subsystem integrates ALU decode logic, execution pipelines, LSU/CSR modules, and cache hierarchies, culminating in a full AXI4-Lite based SoC. 🚀 Each assignment is backed by detailed reports, testbenches, Vivado projects, and hardware debugging via VIO/ILA. 📑📊
Overall, the repository demonstrates complete RTL-to-FPGA design flow and hands-on SoC development experience. 🖥️✨
EE 678 — Repository Info
📦 Repository:
This repository contains coursework deliverables for EE678 Wavelets, focusing on applying wavelet transforms to medical image analysis and MRI-based tumor detection. 🧠📊
The mid-semester work integrates wavelet features into CNN pipelines for improved tumor detection, supported by Python code and a detailed report.
The end-semester project explores wavelet-based deep learning architectures for MRI segmentation, enhancing feature extraction and boundary precision.
Both code modules include preprocessing scripts, wavelet utilities, model architectures, and complete training and evaluation workflows. 💻🔍
Comprehensive reports document the methodology, results, and comparisons across both stages of the course. 📑✨
EE 677 — Repository Info
📦 Repository:
EE677 VLSI CAD involves building CAD tools for digital and quantum circuits, including data-flow graph generation, fault detection through time unrolling, and reversible circuit synthesis.
The repository contains Python implementations for parsing netlists, analyzing circuit structure, and evaluating fault detectability in sequential logic.
Assignments focus on understanding circuit dependencies, modeling stuck-at faults, and automating verification workflows used in practical VLSI CAD systems.
The course project applies Positive Polarity Reed-Muller (PPRM) logic to synthesize reversible circuits, supporting quantum and low-power design methodologies.
These tools demonstrate foundational concepts in graph analysis, fault modeling, Boolean algebra, and algorithmic circuit synthesis.
EE 671 — Repository Info
📦 Repository:
This repository documents the complete EE671 VLSI Design coursework, covering CMOS inverter design, standard-cell layout, RTL synthesis, and full physical design using SkyWater 130A PDK, NGSpice, Magic, Netgen, and OpenLane.
It includes simulations of inverter behavior, DRC/LVS/PEX-verified INVX1 layouts, and synthesis of a 16-bit Wallace Tree adder with functional verification and area/timing reports.
The physical design flow for a 16-bit Brent–Kung adder is captured end-to-end, including CTS, routing, parasitic extraction, and signoff checks with final GDSII outputs.
Project 1 involves developing and characterizing custom standard cells with schematic, layout, LEF/Liberty files, and timing/power analysis.
Project 2 implements a Laplacian edge-detection filter in Verilog, integrating arithmetic blocks and taking the design from RTL to layout with waveform and performance analysis.
Together, these works demonstrate proficiency across device-to-system VLSI workflows, from transistor-level design to full SoC-ready physical implementations.
EE 669 — Repository Info
📦 Repository:
This repository documents my coursework for EE669 VLSI Technology, covering foundational and advanced semiconductor process engineering.
It includes simulations and analysis of oxidation, diffusion, ion implantation, lithography, deposition, etching, and thermal/plasma processing.
Assignments explore crystal anisotropy, Deal–Grove/Massoud oxidation models, dopant diffusion behavior, and lithography artifacts such as standing waves and proximity effects.
The TCAD section features Sentaurus-based simulations for oxide growth, diffusion, trench processes, and ion implantation using SRIM and SProcess.
The repo emphasizes process integration, device scaling trends, and modern device technologies such as FinFETs and GAAFETs.
Together, these works demonstrate hands-on modeling and deep understanding of VLSI fabrication workflows from wafer to device.
EE 451 — Repository Info
EE 344 — Repository Info
📦 Repository:
The EcoSync 8X repository showcases a dsPIC33A-based ultrasonic guided-wave structural health monitoring system with an 8-channel configurable Tx/Rx interface and wireless acquisition using ESP32.
It contains complete firmware for signal generation, command protocols, and Wi-Fi communication, along with full PCB schematics, layouts, component libraries, and laser-cut enclosure files.
The system supports high-voltage Hanning-windowed pulse generation, precision sensing with instrumentation amplifiers, and real-time visualization through a custom GUI.
The documentation includes the bill of materials, step-by-step programming instructions, hardware design workflow, and integration details.
Challenges such as incomplete ADC functionality and partial Wi-Fi–MCU interfacing are described, alongside future plans for GUI enhancements, DI-map improvements, SRAM expansion, and full wireless pipeline completion.
Overall, it demonstrates a complete embedded hardware–software development cycle from concept to prototype.
EE 309 — Repository Info
DH 607 — Repository Info
📦 Repository:
This repository contains assignments and a final project for DH 607, covering probability, statistics, alignment algorithms, HMMs, and RNA-Seq quantification for analyzing real biological datasets.
The coursework builds core skills in quantitative biology through topics such as PCR modeling, BLAST scoring, BWT and suffix structures, and transcript-level expression analysis.
Assignments include probabilistic reasoning, sequence alignment, string algorithms, hidden Markov models, and normalization methods like RPKM and TPM.
The final project performs a multi-omics investigation of Mycobacterium tuberculosis, integrating genomic, transcriptomic, and miRNA data to study disease mechanisms.
It analyzes host immune activation signatures, MTB drug-resistance mutations, and structural modeling of KatG and EmbB variants to explain phenotype-level antibiotic resistance.
Overall, the repository demonstrates a full pipeline of computational biology techniques, from raw sequencing concepts to advanced multi-omics interpretation.