Hi! I'm Amol 👋🏻
I’m a Fourth-Year Dual Degree student in the Electrical Engineering Department at IIT Bombay, specializing in Electronic Systems. I work at the intersection of computer architecture, VLSI design, embedded systems, and intelligent algorithms.
Over the past few years, I’ve built systems that span the entire hardware stack — from transistor-level device modeling and physical design, to full RISC-V SoCs capable of booting Linux, to machine learning pipelines and computational biology workflows.
🧠 What I've Worked On
- Computer Architecture
RISC-V SoCs, OoO superscalar pipelines, caches, branch predictors - VLSI Design & CAD
RTL-to-GDS, process simulation, ROBDDs, ATPG, formal verification - Embedded & FPGA Systems
dsPIC/ESP32 controllers, FPGA SoCs, digital signal pipelines - AI/ML + Signal Processing
wavelet-based segmentation, reinforcement learning, forecasting - Computational Science
multi-omics pipelines, docking simulations, quantum algorithms
🔧 Systems & Architecture Experience
I’ve implemented full RISC-V systems—from microarchitectures to SoC boot flows. My key work includes building a complete RISC-V SoC around the KianV core with SV32 virtual memory, implementing multicycle CPU control, integrating peripherals (UART, GPIO, SDRAM, SPI Flash, CLINT), and successfully booting Linux on FPGA using OpenSBI and U-Boot.
I’ve also designed OoO superscalar processors with ROB, reservation stations, speculative execution, physical-register files, and full hazard-handling logic, along with in-order superscalar VERILOG/VHDL pipelines based on scoreboarding.
⚙️ VLSI, CAD & Fabrication
My VLSI work spans device physics, RTL design, and physical implementation. I’ve simulated fabrication steps (oxidation, diffusion, implantation) using Sentaurus, SRIM/TRIM, NanoHUB, studied advanced nodes (FinFET/GAAFET), and analyzed models like Deal–Grove and Massoud.
On the CAD side, I’ve built systems using ROBDDs, ATPG (minisat), equivalence checking, deductive fault simulation, and designed circuits via Aa(Algorithmic Assembly)→VHDL workflows. I’ve also completed full RTL-to-GDS flows in OpenLane using SkyWater 130nm PDK including synthesis, place-route, DRC/LVS, and Liberty/LEF generation.
📡 Embedded Systems & Hardware Design
I’ve designed full embedded systems such as EcoSync 8X, an ultrasonic SHM device with dsPIC33A, ESP32 pipelines, custom PCBs, and enclosure design. My coursework includes extensive MCU development (8051, dsPIC), analog design (filters, log amplifiers), and biomedical instrumentation (ECG amplifier).
🧬 AI, Computational Science & Machine Learning
I’ve applied ML and signal processing techniques to diverse problems—from wavelet-enhanced U-Net architectures for MRI segmentation to Monte Carlo simulations for option pricing, and multi-omics analysis integrating genomic variants and miRNA networks.
My experience also includes deep reinforcement learning (DDQN, Monte Carlo ES), chess engines, and quantum algorithms, including VQE, Grover’s, Simon’s, Shor’s, and teleportation protocols.
📘 Complete Project Portfolio
You can find my full list of academic and research projects here:
➡️ View All Projects
➡️ View Hackathons